VHDL programming by example /
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| Main Author: | |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
New York :
McGraw-Hill,
[2002]
|
| Edition: | 4th ed. |
| Series: | McGraw-Hill's AccessEngineering.
|
| Subjects: | |
| Online Access: | https://www.accessengineeringlibrary.com/content/book/9780071400701 |
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| 001 | ccn00214102 | ||
| 005 | 20070427182034.0 | ||
| 006 | m f d | ||
| 007 | cr cn ---uuauu | ||
| 008 | 070427s2002 nyua fo 001 0 eng d | ||
| 010 | |z 2002070962 | ||
| 020 | |a 0071455841 | ||
| 020 | |z 0071400702 (print) | ||
| 020 | |a 9780071400701 | ||
| 050 | 4 | |a TK7885.7 |b .P47 2002 | |
| 082 | 0 | 4 | |a 621.39/2 |2 21 |
| 100 | 1 | |a Perry, Douglas L. | |
| 245 | 1 | 0 | |a VHDL |h [electronic resource] : |b programming by example / |c Douglas L. Perry. |
| 250 | |a 4th ed. | ||
| 260 | |a New York : |b McGraw-Hill, |c [2002] | ||
| 300 | |a 1 electronic text (xvii, 476 p.) : |b ill. | ||
| 490 | 1 | |a McGraw-Hill's AccessEngineering | |
| 500 | |a Print version c2002. | ||
| 500 | |a Includes index. | ||
| 505 | 0 | |u http://www.loc.gov/catdir/toc/mh023/2002070962.html | |
| 530 | |a Also issued in print and PDF version. | ||
| 545 | 0 | |a Contributor biographical information |u http://www.loc.gov/catdir/bios/mh041/2002070962.html | |
| 588 | |a Description based on cover image and table of contents, viewed on April 27, 2007. | ||
| 650 | 0 | |a VHDL (Computer hardware description language) | |
| 650 | 0 | |a Computer simulation. | |
| 650 | 0 | |a Simulation methods. | |
| 650 | 0 | |a Sequential processing (Computer science) | |
| 650 | 0 | |a Abstract data types (Computer science) | |
| 650 | 0 | |a Subroutines (Computer programs) | |
| 650 | 0 | |a Configuration. | |
| 650 | 0 | |a System design. | |
| 650 | 0 | |a Microprocessors |x Design and construction. | |
| 650 | 0 | |a RTL (Computer program language) | |
| 650 | 0 | |a Debugging in computer science. | |
| 655 | 0 | |a Electronic books. | |
| 655 | 0 | |a Internet resources. | |
| 740 | 0 | 2 | |a Introduction to VHDL. |
| 740 | 0 | 2 | |a Behavioral modeling. |
| 740 | 0 | 2 | |a Sequential processing. |
| 740 | 0 | 2 | |a Data types. |
| 740 | 0 | 2 | |a Subprograms and packages. |
| 740 | 0 | 2 | |a Predefined attributes. |
| 740 | 0 | 2 | |a Configurations. |
| 740 | 0 | 2 | |a Advanced topics. |
| 740 | 0 | 2 | |a Synthesis. |
| 740 | 0 | 2 | |a VHDL synthesis. |
| 740 | 0 | 2 | |a High-level design flow. |
| 740 | 0 | 2 | |a Top-level system design. |
| 740 | 0 | 2 | |a CPU: synthesis description. |
| 740 | 0 | 2 | |a CPU: RTL simulation. |
| 740 | 0 | 2 | |a CPU design: synthesis results. |
| 740 | 0 | 2 | |a Place and route. |
| 740 | 0 | 2 | |a CPU: VITAL simulation. |
| 740 | 0 | 2 | |a Speed debugging techniques. |
| 830 | 0 | |a McGraw-Hill's AccessEngineering. | |
| 856 | 4 | 0 | |u https://www.accessengineeringlibrary.com/content/book/9780071400701 |
| 949 | |a TK 7885.7 .P47 |w LC |c 1 |i 214102-2001 |d 1/2/2012 |l MAIN |m MGH |q 7 |r Y |s Y |t WEB |u 4/27/2007 |x ENG | ||
| 997 | |a (c)2007 Cassidy Cataloguing Services, Inc. | ||